1. Field
Exemplary embodiments of the present invention relate to a non-volatile memory device, and a fabrication method thereof, and more particularly, to a non-volatile memory device having a three-dimensional (3D) structure where a plurality of memory cells are stacked perpendicularly to a substrate, and a method for fabricating the non-volatile memory device.
2. Description of the Related Art
A non-volatile memory device is a memory device that retains data stored therein even if a power supply is cut off. Diverse non-volatile memory devices such as a flash memory are available.
As the integration degree of a memory device having a two-dimensional structure where memory cells are formed in a single layer over a substrate is reaching physical limits, a non-volatile memory device having a three-dimensional (3D) structure where a plurality of memory cells are stacked along the channels extending from a silicon substrate in a vertical direction and selection transistors are disposed in the upper or lower portions of the memory cells is being developed.
As to the two-dimensional non-volatile memory device, it performs an erase operation where holes are supplied to channels by applying an erase voltage to substrate bodies. As to the three-dimensional non-volatile memory device, while it has channels formed in the shape of pillars extending from a substrate, the three-dimensional non-volatile memory device does not have the layer corresponding to the substrate bodies in the two-dimensional non-volatile memory device. Here, the three-dimensional non-volatile memory device does not perform an erase operation by applying an erase voltage to substrate bodies.
Instead, the three-dimensional non-volatile memory device may perform the erase operation by using selection transistors and causing Gate Induced Drain Leakage (GIDL) to supply holes to the channels.
However, when an erase operation is performed based on the GIDL method, it is difficult to generate a sufficient amount of holes for performing the erase operation because a GIDL occurring region is limited to an area adjacent to a gate edge of a selection transistor. Therefore, it is hard to sufficiently supply holes to channels and accordingly, the speed of an erase operation may deteriorate. Such a feature becomes even more pronounced as the channels become longer.